L3 cache is generally in or controlled by the chipset. (but it'll be off-die on processors soon enough - then the chipset's will be L4. :bugeyes  The BIOS is written to handle it since it may or may not be significant. Share chipsets or at least chipset series, and the code has to handle it. Shared code.
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There are a vast number of people who are uninformed and heavily propagandized, but fundamentally decent. The propaganda that inundates them is effective when unchallenged, but much of it goes only skin deep. If they can be brought to raise questions and apply their decent instincts and basic intelligence, many people quickly escape the confines of the doctrinal system and are willing to do something to help others who are really suffering and oppressed." -Manufacturing Consent: Noam Chomsky and the Media, p. 195
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