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#3 (permalink) | |
Psycho
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Quote:
Oh, that's nice. static CMOS is tried and true. Dynamic logic is basically you split it up into two stages, precharge and discharge, and its called dynamic because you 'precharge' the internal (low-impedance) node to 1 (VDD) and then it either remains at VDD or goes to ground depending on your logic. Dynamic is fast because you only need to have either a pull-up or pull-down network, not both like static CMOS. Of course, the constant act of precharging means a lot of energy, which is why dynamic is reserved for only the most speed-critical tasks. |
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#4 (permalink) |
Very Insignificant Pawn
Location: Amsterdam, NL
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I understand about half of that :-)
It would be more efficient to charge only when needed. (sorta the reverse of what you described). Duh. I suppose the precharge takes place before the logic is tested (precharge) and to just discharge as needed is fast. Duh again. I wonder how much current is required for this family compared to TTL or Cmos. This page seems to describe and compare the families. http://www.equars.com/~marco/poli/phd/node10.html I can follow some of it :-) |
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Tags |
family, favorite, logic |
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