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Old 12-07-2004, 06:16 AM   #13 (permalink)
bendsley
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Quote:
This is wrong. An instruction on a CISC arch like x86 has a variable number of bits per instruction, MMX instructions are far more than 32-bits, and the smallest instructions I believe are above 8-bits.
aoeuhtns:
As I said at the beginning of the article, I didn't want to go too in depth.
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The "abbreviated" lifecycle of an instruction

The basic action of any microprocessor as it moves through the instruction stream can be broken down into a series of four simple steps, which each instruction in the code stream goes through in order to be executed:

1. Fetch the next instruction from the address stored in the program counter.
2. Store that instruction in the instruction register and decode it, and increment the address in the program counter.
3. Execute the instruction currently in the instruction register. If the instruction is not a branch instruction but an arithmetic instruction, send it to the proper ALU.

a. Read the contents of the input registers.
b. Add the contents of the input registers.

4. Write the results of that instruction from the ALU back into the destination register.

In a modern processor, the four steps above get repeated over and over again until the program is finished executing. These are, in fact, the four stages in a classic RISC pipeline. (I'll define the term "pipeline" shortly; for now, just think of a pipeline as a series of stages that each instruction in the code stream must pass through when the code stream is being executed.) Here are the four stages in their abbreviated form, the form in which you'll most often see them:

1. Fetch
2. Decode
3. Execute
4. Write (or "write-back")

Each of the above stages could be said to represent one phase in the "lifecycle" of an instruction. An instruction starts out in the fetch phase, moves to the decode phase, then to the execute phase, and finally to the write phase. Each phase takes a fixed, but by no means equal, amount of time. In the "example processor" I'm thinking of, all four phases take an equal amount of time; this is not usually the case in real-world processors. In any case, if a simple example processor takes exactly 1 nanosecond to complete each stage, then the that processor can finish one instruction every 4 nanoseconds.

Side note: If there is someone that wants a much better explanation of 64bit processors, I will be more than happy to divvy something up.
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Last edited by bendsley; 12-07-2004 at 06:21 AM..
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